Clock and data recovery (CDR) circuits are used in high-speed receivers to recover timing information from an incoming data signal. Many clock and data recovery circuits are predicated upon a basic design designated 101 in FIG. 1. An incoming data signal is received via an external signaling path 103, here a pair of differential conductors, and is processed to extract the recovered clock 105 and individual data symbols. A sampling clock 111 times sampling of the incoming data signal by a first sampler 113 to occur at the approximate middle of a “data eye” associated with each symbol. The first sampler 113 outputs data samples as signal 119 representing these symbols. A second sampler 115 receives an edge clock, which in this case is the recovered clock 105, and this second sampler outputs a signal 117 representing discrete edge samples. Responsive to these edge and data samples, 117 and 119, logic 121 identifies logic level transitions between adjacent symbols, and then advances or delays the recovered clock so as to align it with those transitions. That is, the CDR logic identifies changes in symbol value (e.g., 0-1 or 1-0 for successive bits in a binary signaling scheme) and triggers use of the voltage sample taken at exact transition time with an expected transition voltage mid-point. For example, assuming a signal that crosses a threshold (Th) at the midpoint of a transition, a clock recovery circuit would expect to see edge samples at precisely Th volts for a properly aligned recovered clock; any deviation from this threshold would instead indicate that the recovered clock was early or late, depending on the direction of transition. If, for example, symbol transition were from binary “1” (positive voltage on a specific signal path) to a binary “0” (negative voltage on the specific signal path), a positive voltage edge sample would indicate that the recovered clock was early. If the symbol transition were from binary “0” to a binary “1,” this would indicate that the recovered clock was late. If a negative voltage edge sample were taken at a transition from a binary “1” to a binary “0,” this would also indicate that the recovered clock was late. Finally, a positive voltage edge sample at this later transition would indicate the recovered clock was early.
The current trend for high-speed signaling between integrated circuits (ICs) is toward signaling rates well into the Gigahertz range. However, at and above these signaling rates, it becomes difficult to identify logic states of the digital symbols without some form of equalization. Two conventional forms of receiver-based equalization include linear equalization, one common embodiment being continuous-time linear equalization (CTLE), and decision feedback equalization (DFE); these are each indicated in FIG. 1 by the presence of respective CTLE and DFE circuits 123 and 125. A CTLE circuit 123 is typically used to boost high frequencies relative to low frequencies and thus flatten the channel response (i.e., to counteract the AC attenuation prevalent in wired signaling systems). A DFE circuit 125 instead of flattening the frequency response simply removes the ISI present from the previous data symbol. A DFE circuit can also be used to negate long-latency reflections in the signaling line that closely correlate with previously received data. The DFE 125 circuit is for this reason illustrated in dashed-lines to indicate that it is only sometimes present in these very high-speed signaling systems.
Unfortunately, while some form of equalization is usually needed to recover data at high signaling rates, such equalization is not necessarily helpful for clock recovery. What is needed is an improved equalization technique for clock recovery. Further still, what is needed is a more accurate clock and data recovery technique usable at high signaling rates. The present technology satisfies these needs and provides further, related advantages.
The subject matter defined by the enumerated claims may be better understood by referring to the following detailed description, which should be read in conjunction with the accompanying drawings. This description of one or more particular embodiments, set out below to enable one to build and use various implementations of the technology set forth by the claims, is not intended to limit the enumerated claims, but to exemplify their application to certain methods and devices. The description set out below exemplifies (i) a split-path equalizer, (ii) an improved clock recovery circuit that uses split-path equalization for enhanced clock recovery, (iii) an integrated circuit having one or more such split path equalizers and/or clock recovery circuits, and (iv) related methods, devices and systems. While the specific examples are presented, the principles described herein may also be applied to other methods, devices and systems as well.